The present invention generally relates to the structure of a semiconductor memory device which enables a high operation speed even in a high-capacity semiconductor memory device.
FIG. 11 partially shows memory cell arrays of a conventional, typical semiconductor memory device. The semiconductor memory device of FIG. 11 includes memory cell arrays 1a to 1d, a local word line 10, bit line pairs (40a, 40b), (41a, 41b), (42a, 42b), (43a, 43b) and a global word line 20. Each memory cell array 1a to 1d includes a multiplicity of memory cells arranged in row and column directions. The local word line 10 is formed from a relatively high resistance material, and selects the memory cells arranged in the row direction in the memory cell arrays 1a to 1d. The bit line pair (40a, 40b), (41a, 41b), (42a, 42b), (43a, 43b) transmits the memory cell data to a sense amplifier in the subsequent stage. The global word line 20 is formed from a relatively low resistance material, and connected to the local word line 10 at intervals of an arbitrary number of memory cell arrays.
In the conventional structure, however, the number of memory cells in the row direction and thus the load capacity of the word line are increased in proportion to the capacity of the memory cell arrays 1a to 1d. Such increased load capacity hinders rapid activation of the word line, increasing access delay.
It is an object of the present invention to implement an improved operation speed even in a high-capacity semiconductor memory device.
In order to achieve the above object, the present invention uses a substantially reduced number of memory cells connected per global word line.
More specifically, a semiconductor memory device of the present invention includes: a memory cell array including a plurality of memory cells arranged in a matrix in row and column directions; a local word line for selecting memory cells in the row direction of the memory cell array; a bit line pair for transmitting data of memory cells in the column direction of the memory cell array; and a plurality of global word lines connected to the local word line, and formed in a wiring layer located higher than that of the local word line. The plurality of global word lines are formed in at least two different wiring layers.
Preferably, the plurality of global word lines are formed on the memory cells arranged in the row direction of the memory cell array.
Preferably, of the plurality of global word lines, a global word line formed in an upper layer is connected to the local word line at a prescribed junction, and a global word line formed in a lower layer extends toward inside or outside of the memory cell so as to bypass the junction between the global word line in the upper layer and the local word line.
Preferably, the global word line formed in the lower layer bypasses the junction in a memory cell that is located adjacent to a memory cell of the junction in the row direction.
Preferably, at least two local word lines are arranged in a same row. Of the plurality of global word lines, a global word line formed in an upper layer is connected to one of the two local word lines, and a global word line formed in a lower layer is connected to the other local word line.
Preferably, the memory cell array includes at least two memory cell array blocks in the column direction. The local word line is divided into at least two lines corresponding the respective memory cell array blocks. The plurality of global word lines are connected to at least one of the local word lines.
Preferably, of the plurality of global word lines, a global word line formed in an upper layer is connected to a local word line of one of the at least two memory cell array blocks located further from a word line driver.
Preferably, the above semiconductor memory device further includes a spare memory cell for replacing a defective memory cell. The spare memory cell is connected to at least one of the plurality of global word lines.
Preferably, the above semiconductor memory device further includes: a precharge transistor for precharging a potential on each bit line of the bit line pair to a prescribed value; and a plurality of precharge control lines for controlling the precharge transistor. The plurality of precharge control lines are formed in at least two different wiring layers.
According to the present invention, a plurality of global word lines are arranged in the row direction. This reduces the number of memory cells connected per global word line, enabling rapid activation of the word line. Moreover, the plurality of global word lines are formed in at least two different wiring layers. This reduces coupling capacity between the global word lines. As a result, the time constant of the word line is reduced, whereby rapid activation of the word line is achieved more effectively.
According to the present invention, the plurality of global word lines are formed on the memory cells of the memory cell array. As a result, a compact semiconductor device is implemented without increasing the size of the memory cell array.
According to the present invention, the plurality of global word lines are formed in a wiring layer located higher than that of the word line. If the plurality of global word lines are formed in two different wiring layers (e.g., upper and lower layers), the global word line formed in the lower layer would interfere with a through hole or the like at the junction between the global word line formed in the upper layer and the word line. In the present invention, however, the global word line formed in the lower layer extends toward the inside or outside of the memory cell so as to bypass the junction. Therefore, the global word lines can be arranged in the memory cell array without increasing the size of the memory cell array.
Moreover, according to the present invention, adjacent two global word lines formed in different wiring layers are connected to different local word lines. This reduces coupling capacity between the adjacent global word lines, allowing for reduced operation delay of the word line.
Moreover, according to the present invention, a global word line is connected to, e.g., a local word line of a single memory cell array block, and another global word line is connected to, e.g., the local word lines of all the memory cell array blocks. Accordingly, only a word line of a specific block can be accessed by selecting a global word line to be activated. This allows for reduced power consumption.
Moreover, according to the present invention, the local word line of the memory cell array block located further from the word line driver is connected to the global word line formed in the upper layer, i.e., the global word line extending straight without interfering with the global word line formed in the lower layer. This enables reduction in critical operation delay in the memory cell array block located further from the word line driver.
Moreover, according to the present invention, the spare memory cell is connected to at least one of the plurality of global word lines. This enables rapid access to the spare memory cell.
Moreover, according to the present invention, a plurality of precharge control lines are formed in at least two different layers. This reduces coupling capacity between the precharge control lines, and also enables rapid activation of the precharge control line. As a result, the precharge transistor can be driven rapidly, enabling an improved precharging speed.